DBG_DEF(DBGID_MCE_ROM_BANK0_ASM_361, 3, DBGCH2, 2, "BLE TX Access Address %2x %2x", "mce_rom_bank0.asm", 361)
DBG_DEF(DBGID_MCE_ROM_BANK0_ASM_421, 4, DBGCH2, 2, "RF Channel Mismatch. (Got %1d, expected %1d)", "mce_rom_bank0.asm", 421)
DBG_DEF(DBGID_MCE_ROM_BANK0_ASM_530, 5, DBGCH2, 0, "1MBAUD RX packet completed", "mce_rom_bank0.asm", 530)
DBG_DEF(DBGID_MCE_ROM_BANK0_ASM_613, 6, DBGCH2, 0, "2MBAUD RX packet completed", "mce_rom_bank0.asm", 613)
DBG_DEF(DBGID_MCE_ROM_BANK1_ASM_478, 7, DBGCH2, 0, "Sync found", "mce_rom_bank1.asm", 478)
DBG_DEF(DBGID_MCE_ROM_BANK2_ASM_439, 8, DBGCH2, 0, "MRX 5 Mbps. RFE is active, starting DC calibration", "mce_rom_bank2.asm", 439)
DBG_DEF(DBGID_MCE_ROM_BANK2_ASM_542, 9, DBGCH2, 1, "Sync Found. CPE reports packet length (in bits): %d", "mce_rom_bank2.asm", 542)
DBG_DEF(DBGID_MCE_ROM_BANK2_ASM_565, 10, DBGCH2, 0, "Notifying RFE of end of packet", "mce_rom_bank2.asm", 565)
DBG_DEF(DBGID_MCE_ROM_BANK3_ASM_214, 11, DBGCH2, 1, "LRM K=7 FEC TX Mode, DSSS = %d", "mce_rom_bank3.asm", 214)
DBG_DEF(DBGID_MCE_ROM_BANK3_ASM_272, 12, DBGCH2, 0, "LRM 64-bit 0xFE6B_2840_0194_D7BF (LSB first) SyncWord Sent", "mce_rom_bank3.asm", 272)
DBG_DEF(DBGID_MCE_ROM_BANK3_ASM_299, 13, DBGCH2, 0, "FEC TX. Starting termination sequence", "mce_rom_bank3.asm", 299)
DBG_DEF(DBGID_MCE_ROM_BANK3_ASM_375, 14, DBGCH2, 1, "LRM K=7 FEC RX Mode, DSSS = %d", "mce_rom_bank3.asm", 375)
DBG_DEF(DBGID_MCE_ROM_BANK3_ASM_412, 15, DBGCH2, 0, "Waiting for Sync....", "mce_rom_bank3.asm", 412)
DBG_DEF(DBGID_MCE_ROM_BANK3_ASM_445, 16, DBGCH2, 2, "Sync found. DC Offset in SFD is %d, Sync Word Match Value(One Sample after max peak) %d", "mce_rom_bank3.asm", 445)
DBG_DEF(DBGID_MCE_ROM_BANK3_ASM_549, 17, DBGCH2, 0, "LRM. Packet Completed!", "mce_rom_bank3.asm", 549)
DBG_DEF(DBGID_MCE_ROM_BANK4_ASM_182, 18, DBGCH2, 0, "MCFG - GenericFSK - rom bank 4", "mce_rom_bank4.asm", 182)
DBG_DEF(DBGID_MCE_ROM_BANK4_ASM_360, 19, DBGCH2, 0, "GenericFSK, NoFEC, TX Started", "mce_rom_bank4.asm", 360)
DBG_DEF(DBGID_MCE_ROM_BANK4_ASM_1151, 20, DBGCH2, 0, "Halting RX", "mce_rom_bank4.asm", 1151)
DBG_DEF(DBGID_MCE_ROM_BANK4_ASM_1184, 21, DBGCH2, 0, "All bits received, MCE Ending", "mce_rom_bank4.asm", 1184)
DBG_DEF(DBGID_MCE_ROM_BANK4_ASM_1205, 22, DBGCH2, 0, "GenericFSK, NoFEC, RX Started", "mce_rom_bank4.asm", 1205)
DBG_DEF(DBGID_MCE_ROM_BANK4_ASM_1236, 23, DBGCH2, 1, "Sync found, MAFC = %d", "mce_rom_bank4.asm", 1236)
DBG_DEF(DBGID_MCE_ROM_BANK4_ASM_1243, 24, DBGCH2, 2, "Synced to SW B. Sync Match %d before peak and %d after peak", "mce_rom_bank4.asm", 1243)
DBG_DEF(DBGID_MCE_ROM_BANK4_ASM_1248, 25, DBGCH2, 2, "Synced to SW A. Sync Match %d before peak and %d after peak", "mce_rom_bank4.asm", 1248)
DBG_DEF(DBGID_MCE_ROM_BANK5_ASM_196, 26, DBGCH2, 0, "MCFG - MCE rom bank 5", "mce_rom_bank5.asm", 196)
DBG_DEF(DBGID_MCE_ROM_BANK5_ASM_396, 27, DBGCH2, 0, "SOFTTX, TX Started, Enables Manchester Coding", "mce_rom_bank5.asm", 396)
DBG_DEF(DBGID_MCE_ROM_BANK5_ASM_462, 28, DBGCH2, 0, "GenericFSK, 4ary, NoFEC, TX Started", "mce_rom_bank5.asm", 462)
DBG_DEF(DBGID_MCE_ROM_BANK5_ASM_1175, 29, DBGCH2, 0, "Halting RX", "mce_rom_bank5.asm", 1175)
DBG_DEF(DBGID_MCE_ROM_BANK5_ASM_1209, 30, DBGCH2, 0, "All bits received, MCE Ending", "mce_rom_bank5.asm", 1209)
DBG_DEF(DBGID_MCE_ROM_BANK5_ASM_1228, 31, DBGCH2, 0, "Soft RX, Manchester coding, RX Started", "mce_rom_bank5.asm", 1228)
DBG_DEF(DBGID_MCE_ROM_BANK5_ASM_1302, 32, DBGCH2, 1, "MCE ending, FIFO has received %d bits ", "mce_rom_bank5.asm", 1302)
DBG_DEF(DBGID_MCE_ROM_BANK5_ASM_1317, 33, DBGCH2, 0, "GenericFSK, NoFEC, RX Started", "mce_rom_bank5.asm", 1317)
DBG_DEF(DBGID_MCE_ROM_BANK5_ASM_1351, 34, DBGCH2, 1, "Sync found, MAFC = %d", "mce_rom_bank5.asm", 1351)
DBG_DEF(DBGID_MCE_ROM_BANK5_ASM_1358, 35, DBGCH2, 2, "Synced to SW B. Sync Match %d before peak and %d after peak", "mce_rom_bank5.asm", 1358)
DBG_DEF(DBGID_MCE_ROM_BANK5_ASM_1363, 36, DBGCH2, 2, "Synced to SW A. Sync Match %d before peak and %d after peak", "mce_rom_bank5.asm", 1363)
